Pulse count mode communication system

ABSTRACT

PCT No. PCT/JP90/01613 Sec. 371 Date Jul. 24, 1991 Sec. 102(e) Date Jul. 24, 1991 PCT Filed Dec. 11, 1990 PCT Pub. No. WO91/09362 PCT Pub. Date Jun. 27, 1991.A transmitter pulse circuit produces two-phase pulse trains containing a certain number of pulse edges corresponding to an integral number represented by binary parallel bits of a data value to be transferred. The transmitter responds to a coordinate data value derived from a digitizer. The receiver includes a counter for counting pulse edges contained in the two-phase pulse trains, and a retrieving circuit for retrieving intermittently the counted contents to determine the number of received pulse edges. The counting circuit and the retrieving circuit constitute together a bus mouse interface of a host computer in the receiver. The coordinate data can be transferred to the host computer through the bus mouse interface without using a general RS-232C interface, thereby efficiently improving the host computer multiple terminal processing capacity.

TECHNICAL FIELD

The present invention generally relates to a communication system fortransferring data composed of binary parallel bits from a transmitter toa receiver, and specifically relates to a system for transferring aninput data value from a peripheral terminal device to a host computer toprocess the data. More particularly, the present invention relates to acommunication system for transferring a coordinate data value derivedfrom a digitizer operative to effect two-dimensional coordinatedesignation to a host computer through an interface provided in the hostcomputer.

BACKGROUND TECHNOLOGY

A conventional asynchronous data communication system operating in astart-stop synchronization mode initially converts parallel data bitsinto serial data bits which are then transferred, i.e. transmitted, froma transmitter to a receiver.

This system is described briefly with respect to an example in which adata value is transferred from a digitizer to a host computer. FIG. 10is an overall perspective view of a communication system including adigitizer and a host computer. The digitizer 1 is comprised of a tabletplanar sensor 2 which defines a two-dimensional coordinate plane. Asuitable input tool such as a stylus pen 3 is used to designate a givenpoint on a surface of the tablet planar sensor 2 so that the sensor 2generates an analog detection signal indicative of the designated point.The digitizer 1 further includes a processing circuit unit operative tocalculate data representative of a two-dimensional coordinate value ofthe designated point according to the analog detection signal. Thecalculated data are fed to the host computer 5 through a signal cable 4.The host computer 5 is provided with a plurality of different typeinterfaces for connection with peripheral input and output terminaldevices. The interfaces are selected according to a form of the signalto be transferred.

FIG. 11 is a waveform of an output signal transmitted from thedigitizer. For example, the digitizer generates a coordinate data valuein the form of eight parallel data bits. This eight-bit parallel datavalue is subjected to parallel/serial conversion to produce an eight-bitserial data signal as shown in FIG. 11. For example, eight parallel databits represented by 10110101 are converted into a correspondingeight-bit serial data signal represented by 1-0-1-1-0-1-0-1. Such modeof bit data transmission is called an asynchronous system of start-stopsynchronization mode as noted before. In order to receive a data signalformed according to the asynchronous system of start-stopsynchronization mode, the host computer is typically provided with aparticular interface based on an RS-232C standard. Therefore, aperipheral terminal device is generally connected to the host computerthrough a general purpose RS-232C interface.

The RS-232C interface is normally shared by various kinds of peripheralterminal devices adopted to execute data transfer or transactionaccording to the asynchronous system of start-stop synchronization mode.However, the RS-232C interface can accept a limited number of peripheralterminal devices to be concurrently accessed by the host computer.Therefore, it is desired to provide a different communication mode foreffectively executing data transfer or transaction through otherinterfaces of the host computer than the RS-232C interface.

The typical host computer is provided with a bus mouse interfacespecifically designed to be connected to a bus mouse device. A briefdescription is given herewith for the bus mouse for facilitatingunderstanding of the present invention. A bus mouse is generallyutilized as a coordinate input terminal device for a computer. However,the bus mouse can treat only a relative displacement value. Further,since the bus mouse has an overall size considerably greater than astylus pen used as an input tool of the digitizer, the bus mouse cannotcarry out character input and menu selection. On the other hand, thedigitizer can treat the absolute coordinate value and input characters.Since the bus mouse has a relatively low price and utilizes a relativelysimple interface construction, recently developed computers aregenerally compatible with a standard bus mouse. FIG. 12 is a schematicdiagram of the construction of a typical bus mouse device. The bus mouseis manually moved to derive input computer signals representing theamount of its own displacement. The bus mouse is provided on its bottomportion with a ball member 6 to enable the movement of the body of thebus mouse. A pair of sensors 7 and 8 are disposed in contact with theball member 6 to detect separately X-axis and Y-axis components of thedisplacement amount.

FIG. 13 is a schematic illustration for the operation of the bus mousesensor of FIG. 12. The X-axis sensor 7 has a rotary shaft in contactwith the ball member 6. Although not shown in the figure, Y-axis sensor8 has another rotary shaft disposed orthogonally to the rotary shaft ofthe X-axis sensor 7, in contact with the ball member 6. As ball 6 rollsdue to the displacement of the bus mouse, the rotary shaft of the X-axissensor 7 is rotated according to the X-axis component of thedisplacement to produce an output signal having pulse trains XA and XB.Concurrently, the bus mouse outputs a switching signal S1 and S2indicative of operating state or condition of the bus mouse.

FIG. 14 represents waveforms for output signals of the bus mouse. Asshown in the figure, the output signal is composed of two pulse trains.When the bus mouse is displaced in the plus or positive direction interms of X-axis, pulse train XA has a leading phase with respect topulse train XB. On the other hand, when the bus mouse is displaced inthe minus or negative direction in terms of X-axis, the pulse train XAhas a lagging phase with respect to pulse train XB. By such operation,the amount of bus mouse displacement per unit time is detected in termsof a number of pulse edges per unit time contained in the output signal;the displacement direction is indicated by the relative phase conditionof the output signal.

The typical host computer is provided with a bus mouse interfaceresponsive to the output and switching signals from a bus mouse device.The bus mouse interface contains first and second eight-bit countersrespectively corresponding to the X and Y coordinates for counting pulseedges of the X and Y output signals. These calculation results areretrieved from the respective eight-bit counters each period of a giveninterval of, e.g., 8 ms, regulated by an internal time in the hostcomputer to detect the amount of bus mouse displacement and the switchcondition of the bus mouse every period.

As shown in FIG. 11, a conventional digitizer produces an output signalcomposed of a binary bit series according to the asynchronous system ofstart-stop synchronization mode. On the other hand, as shown in FIG. 14,the bus mouse device produces an output signal composed of a two-phasepulse train. Therefore, the conventional digitizer has a differentoutput signal format from that of the bus mouse device. Hence thedigitizer cannot be directly connected to the bus mouse interface of thehost computer.

As understood from the above description, the binary bit serial datavalue cannot be supplied to the bus mouse interface of the hostcomputer, if it is based on the asynchronous system of start-stopsynchronization mode. However, the bus mouse interface is so specializedand therefore is not as frequently occupied as the general RS-232Cinterface. Thus, it is desired in commercial use to carry out the datatransfer or transactions by using a channel of the bus mouse interface.However, the conventional data communication system could not satisfysuch a demand in the market.

In view of the above noted drawbacks of the conventional datacommunication system, an object of the present invention is to provide anew communication system for transferring parallel data bits from atransmitter, such as a peripheral terminal device, to a receiver, suchas a host computer, through a bus mouse interface provided in the hostcomputer.

DISCLOSURE OF THE INVENTION

In the inventive communication system for transferring serial data ofbinary bits from a transmitter to a receiver, the transmitter isprovided with a pulse circuit which operates each transfer period of agiven interval to output a two-phase pulse train containing a certainnumber of pulse edges according to an integral value represented by thebinary bits to be transferred. This transmitter transmits, for example,a two-dimensional coordinate data value inputted from a digitizer. Onthe other hand, the receiver is provided with a counting circuit forcounting a number of pulse edges contained in the two-phase pulse train,and a retrieving circuit operative each transfer period forintermittently retrieving and resetting a constant of the countingcircuit at a given sampling interval and being operative when the newestretrieved content becomes null for summing up all of the successivelyretrieved contents to thereby determine the number of received pulseedges within each transfer period. The counting and retrieving circuitsconstitute a bus mouse interface in the receiver.

According to the inventive pulse count mode communication system, thedata value is transferred to the host computer through the bus mouseinterface instead of the RS-232C interface, in contrast to the priorart. Therefore, multiplex terminal processing capacity of the hostcomputer can be efficiently utilized to a greater extent and thespecialized bus mouse interface can be extensively utilized compared tothe prior art.

In a preferred form, the transmitter includes a coding circuit forapplying to each data value either a plus or minus code to discriminatea sequence of plural data values from each other. The pulse circuitoperates according to the applied code to switch a phase condition ofthe two-phase pulse train. On the other hand, the receiver operatesaccording to the phase switching of the two-phase pulse train todiscriminate from each other the time-sequentially transferred pluraldata values. The coding circuit applies, for example, the plus and minuscodes alternately to the sequence of the plural data values. Otherwise,the coding circuit applies the other code to the remaining subsequentdata values. By such coding, data transaction errors can be effectivelyavoided.

In another preferred form, the transmitter includes a pair of the pulsecircuits for concurrently transmitting a pair of data values, and thereceiver includes a pair of corresponding counting circuits forconcurrently receiving the pair of data values. The pair of pulsecircuits operate, for example, to transmit a packet of four data valueseach transaction process by outputting a pair of data values during afirst transfer period and outputting another pair of data values duringa second transfer period, thereby improving data transaction rate.

In a further preferred form, the receiver includes a selecting circuitoperative to select either an absolute coordinate data value or arelative coordinate data value obtained from a coordinate input device,such as a digitizer, in order to selectively transfer one or the otherof the absolute and received data values. When the relative coordinatedata value is selected, the retrieving circuit of the receiver operatesduring retrieving periods that are shorter than the data transferperiods for detecting each relative coordinate data value derived fromthe transmitter every transfer period. The relative coordinate datavalue is applied with either a positive or a negative sign by the codingcircuit, and thereafter is transmitted as a two-phase pulse train by thepulse circuit in a manner similar to the transfer of the bus mousedisplacement data value. According to the inventive communicationsystem, a coordinate input device can selectively or switchably transfereither the absolute or relative coordinate data value to a host computerthrough the bus mouse interface without using the serial RS-232Cinterface as opposed to the prior art. Therefore, the general purposeserial interface can be assigned to other peripheral devices accordingto their priority. The bus mouse interface conventionally kept specificto the bus mouse device can be efficiently utilized as a commoninterface for the coordinate input device. In addition, the hostcomputer can operate an application program designed for theconventional bus mouse.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an overall structural diagram of the inventive pulse countmode communication system;

FIG. 2 is a waveform diagram of a two-phase pulse train;

FIG. 3 is a data transaction timing chart;

FIG. 4 is another data transaction timing chart;

FIG. 5 is a detailed circuit diagram of a transmitter;

FIG. 6 is a timing chart illustrative of the transmission operation;

FIG. 7 is a waveform diagram of an X two-phase pulse train and a Ytwo-phase pulse train;

FIG. 8 is a block diagram of the receiver;

FIG. 9 is a flow chart of a receiver retrieving operation;

FIG. 10 is a schematic perspective view of the conventionalcommunication system;

FIG. 11 is a waveform diagram of a transfer signal according to theconventional data transaction mode;

FIG. 12 is a schematic structural diagram of the typical bus mouse;

FIG. 13 is an illustrative diagram for the operation of a bus mousesensor;

FIG. 14 is a waveform diagram of a bus mouse output signal;

FIG. 15 is a transfer timing chart for a relative coordinate data value;

FIG. 16 is a detailed circuit diagram of another embodiment of thetransmitter;

FIG. 17 is a timing chart for the operation of a further embodiment ofthe transmitter; and

FIG. 18 is a flow chart of the displacement data transmission process inthe transmitter.

THE BEST MODES FOR PRACTICING THE INVENTION

FIG. 1 is a block diagram of an overall structure of the pulse edgecount mode communication system according to the invention. Thecommunication system is comprised of a pulse data transmitter 9 and apulse data receiver 10. The transmitter 9 is provided with a pulsecircuit 11 operative every transfer period of a given interval to outputa two-phase pulse train containing a certain number of pulse edgeshaving an integral value represented by serial binary bits which form adata value to be transferred.

Receiver 10 is provided with a resettable counting circuit 12 forcounting successive pulse edges contained in the two-phase pulse train,and a retrieving circuit 13 operative each sampling time within onetransfer period for successively retrieving and resetting the content ofthe counting circuit 12 and being operative when the newest retrievedcontent becomes null for summing up all of the retrieved contents todetermine the number of pulse edges supplied to the receiver. Namely,the counting circuit 12 and the retrieving circuit 13 constitute a busmouse interface in the pulse data receiver 10.

Preferably, the transmitter 9 includes a coding circuit 14 forselectively applying to each of a plurality of sequential data values aplus and minus code in order to discriminate the plural data value fromeach other. The pulse circuit 11 operates according to the applied codeto select a phase condition of the two-phase pulse train. In addition,the pulse data receiver 10 operates according to the phase condition todiscriminate the transferred sequential plural data values from eachother. The coding circuit 14 operates, for example, to apply alternatelypositive and negative codes to a sequence of the plural data values todiscriminate preceding and succeeding codes from each other. Otherwise,the coding circuit 14 may apply one code to the first of the sequentialdata values and may apply another code to the remaining subsequent datavalues so that the receiver can detect the transmission starting time ofa packet transaction of multiple data values.

In a preferred form, the pulse circuit 11 comprises an X pulse circuitand a Y pulse circuit so as to transmit a pair of data valuesconcurrently. Correspondingly, the counting circuit 12 is comprised ofan X counting circuit and a Y counting circuit so as to concurrentlyreceive the pair of data values. Moreover, the X and Y pulse circuitsoperate in a first transfer period to transmit a first pair of datavalues and operate in a second transfer period to transmit a second pairof data values to transfer a four data packet by processing onetransaction. Such communication mode is most suitable for transferring apacket of data values indicative of a coordinate point inputted from adigitizer.

In one aspect of the present invention, a communication system utilizesa bus mouse interface for a transaction involving a packet of four datavalues during one transaction processing step. The transmitter outputseach data value in the form of a two-phase pulse train. On the otherhand, the receiver, such as a host computer, is provided with a busmouse interface having the following functions:

1. count a number of pulse edges contained in the two-phase pulse train;

2. detect whether the phase of the two-phase pulse train is advancing orreceding to recognize plus or minus data values; and

3. concurrently count pulse edges contained in a pair of two-phase pulsetrains. The above listed three functions are executed by specifichardware, i.e., a mouse counter provided in the receiver. The receiverconverts the received two-phase pulse train into an eight-bit binarycomplement representation of a decimal data value representing numbersfrom "-128" through "+127". The transmitter transmits each data value asa two-phase pulse train to the receiver by using the above noted threereceiver functions.

If one data value includes seven binary parallel bits, the data valuemay represent an integral value of "0" through "127". In such case, thetransmitter outputs the data value in the form of a two-phase pulsetrain containing a corresponding number of pulse edges from 0 to 127 Forexample, as shown in FIG. 2, if the original data value is 18H, thecorresponding binary parallel bits represent the integer "24" so thatthe produced two-phase pulse train contains 24 pulse edges. Thetwo-phase pulse train is comprised of two phase components XA and XB.The phase relation between the two components is determined according toa code applied to the data. For example, if the data value is appliedwith the plus code, the phase component XA is advanced relative to thephase component XB. On the other hand, if the data value is applied withthe minus code, the phase component XA is delayed relative to the otherphase component XB. The term "pulse edge" indicates leading and trailingedges of a pulse contained in the two-phase pulse train; the number ofpulse edges is determined by counting all of the pulse edges containedin the two-phase pulse train. The receiver counting circuit, i.e., themouse counter, counts pulse edges one by one to accumulate calculatedresults in its register. The receiver retrieving circuit, e.g., CPU,reads out mouse counter content to obtain the data value 18H fed fromthe transmitter. The CPU resets or clears the mouse counter afterreading out the counted content.

If the CPU fails to timely retrieve the counted value from the mousecounter, the counter might overflow during the course of continuousfeeding of the two-phase pulse trains. For example, if the transmittertransmitted the next data value as the value 5 after the transmitter hadtransmitted a previous data value of FF while the receiver failed toretrieve the mouse counter content, the mouse counter would overflowsuch that its content were incorrectly set to the data value 04. Asunderstood from the above description, the data value outputted from thetransmitter would not be correctly received by the receiver. In view ofthis, the retrieving timing of the mouse counter in the receiver shouldbe regulated according to the output timing of the two-phase pulse trainin the transmitter. According to the inventive pulse count communicationsystem, a specific data transfer mode is adopted as shown in FIG. 3 soas to avoid overflow of the mouse counter.

Referring to the data transaction timing chart of FIG. 3, thetransmitter operates during each given 2.5 ms. transfer period to outputa two-phase pulse train (XA, XB) containing a certain number of pulseedges corresponding to an integral value represented by the data valueto be transferred. The receiver operates during every sampling intervalwhich is set smaller than the each transfer period (for example, 1 ms)for intermittently retrieving the content of the mouse counter. Themouse counter is read out and reset successively while the two-phasepulse train is being derived to avoid mouse counter overflow as well asto recognize an output stop state of the two-phase pulse train tothereby separate multiple data value sequences from each other. In theFIG. 3 timing chart, two data values indicative of integral values "40"and "35" are sequentially transferred from the transmitter to thereceiver. When the transmitter starts to output a two-phase pulse traincontaining 40 pulse edges so as to transfer the first data, the CPU ofthe receiver operates at time a to read out the mouse counter. At timea, the CPU retrieves a fragmented content "15" indicative of anintermediate number of the pulse edges already outputted during time a.The mouse counter is reset at time a, while it continues to count pulseedges. At the next time b, the mouse counter is again read out orsampled to retrieve another fragmented content of "25" which representsthe remaining number of the outputted pulse edges. The receiver operatesto sum up the calculated contents retrieved twice to determine the totalnumber of the pulse edges received within one transfer period. At asubsequent time c, the CPU of the receiver again reads the mouse countercontent in the same manner. However, since the output of the pulse trainhas been finished and the mouse counter was reset at the previous sampletime b, the last retrieved content is null. The receiver recognizes thatthe first data value transfer has been finished when the last nullcontent is retrieved from the mouse counter; the receiver determinesthat the summed value of "15+25=40" is a decimal integer representationof the transferred data value.

Subsequently during a second transfer period, there number of pulseedges corresponding to the integral value "35" represented by the seconddata value to be transferred. In this second period, the receiversuccessively reads the mouse counter content at sampling times d, e andf to thereby count and determine the transmitted pulse edge number inthe same manner.

Next, the description is given for a data transaction mode fortransferring a packet of four data values during one transactionprocessing interval by using the continuous data transfer systemdescribed in conjunction with FIG. 3. In this mode, the X and Y mousecounters are used to concurrently transfer a pair of data. By the firsttransaction process, a first pair of data values are transferred withina first transfer period, and a second pair of data values are thentransferred within a second transfer period, thereby effectingtransaction of a packet of four data values.

Since the four data values are treated in one transaction processingoperation, the receiver has to separately recognize individual datavalues. Namely, the receiver has to determine whether a pair of X and Ydata values are transmitted during the first period or the secondperiod. The data values are applied with a plus or minus code in orderto discriminate between the first and second periods. Namely, the plusand minus codes are alternately applied to the X data value of theconcurrently transferred X and Y data values during each transferperiod. The selective application of the plus and minus codes iseffected by switching the phase condition of the corresponding two-phasepulse train. Hence, the receiver detects the phase condition todetermine whether the admitted data value is coded plus or minus. Ifplus, the admitted data pair is of the first period. On the other hand,if minus, the admitted data pair is of the second period, therebydiscriminating four individual data from each other.

In order to ensure the above noted discrimination, the X data value iscoded minus once in the one transaction processing. If the X data valuehas a zero value incidentally when the minus code is to be applied tothat data value, the receiver cannot recognize whether that data valueis associated with the first one or the second one. In view of this,when a zero data bit is outputted incidentally at a time of the minuscoding, the transmitter outputs that zero data value in the form of anegative integer "-128". The receiver operates when the data value isadmitted in the form of "-128" to recognize that the admitted data valueactually represents a zero value. By the above noted communication mode,a packet of the four data values can be communicated during onetransaction processing.

Further, there is proposed another transfer mode as shown in FIG. 4 inorder to improve reliability of the data detection and recognition inthe receiver. Namely, the transmitter operates during the first transferperiod to apply a plus code to the X data value and to apply a minuscode to the Y data value for the first data pair. In turn, thetransmitter operates during the second transfer period to applyreversely a minus code to the X data value and to apply a plus code tothe Y data value. On the other hand, the receiver recognizes that thefour admitted data values are normal and complete when the precedinglyadmitted X data value is positive and the corresponding Y data value isnegative and when the succeedingly admitted X data value is negative andthe corresponding Y data value is positive. The receiver judges if thefour admitted data values are otherwise erroneous. By such operation,the transferred packet of four data values can be regularly checked asto completeness.

The inventive communication system is not limited to the above describedcase where a packet of four data values is transferred by onetransaction proceeding; the inventive system may also be applied toanother case where a packet of eight data values is transferred duringone transaction processing, as indicated by the following TABLE 1.

                  TABLE 1                                                         ______________________________________                                        X DATA       + 0 - 0 + 0 - 0 + 0 -                                            Y DATA       - 0 + 0 + 0 + 0 - 0 +                                            ______________________________________                                    

In the above example, a pair of X and Y pulse circuits successivelytransmit a pair of X and Y data values. The plus or minus code isalternately switched every other transfer period with respect to the Xdata value to discriminate adjacent data pairs from each other. On theother hand, the first or top Y data value of one transaction packet isapplied with a negative code and the remaining or subsequent Y datavalue in the same data packet are applied with the positive code. Thereceiver recognizes that a particular Y data value is the top value inone packet when that Y data value is coded negative. By such manner, thetransmitter and the receiver cooperate in synchronization with eachother to transfer multiple data values. In addition, check sum operationor CRC operation may be effected for the last end data value in one datapacket to check the reliability of the transferred data value.

A detailed description is given infra for one embodiment of theinventive pulse count mode data communication system with reference toFIGS. 5-9. FIG. 5 is a structural diagram of hardware provided in thetransmitter. This hardware includes X pulse circuit 15 and Y pulsecircuit 16 (which correspond, respectively, to an X mouse counter and Ymouse counter in the receiver) and a timing circuit 17 for controllingpulse train transmission timing. The X and Y pulse circuits 15 and 16have the same construction and derive X pulse trains (XA, XB) and Ypulse trains (YA, YB), respectively.

As shown in FIG. 5, the X pulse circuit 15 is comprised of a pulse traingenerating circuit 18 operative according to a numerical valuerepresented by an 8-bit parallel data signal fed through a data bus DBto generate a corresponding primary pulse train, and a phase circuit 19responsive to the primary pulse train to produce an X two-phase pulsetrain (XA, XB). The pulse train generating circuit 18 includes an 8-bitlatching circuit 20 for successively latching data fed from the data busDB, and an 8-bit binary counter 21 responsive to the latched 8-bit datato count (decode) the same to produce a signal CY for gating a clockpulse signal CK through a NAND circuit 28 during a given time intervaldetermined by the received data value for counting the clock pulsesignal CK according to the binary numerical value representing thelatched data value. A definite number of the counted clock pulses is fedin the form of a primary or basic pulse train to the phase circuit 19through a NAND circuit 28. The phase circuit 19 includes a pair ofD-flip-flops 22, 23 operative according to a positive or negative signof the latched data value held in the latching circuit 20 for producingX two-phase pulse train (XA, XB) having a relative leading or delayingphase condition.

FIG. 6 is a timing chart illustrative of the operation of the FIG. 5circuit. In this embodiment, the clock pulse signal CK has a 2 μs periodbetween adjacent pulse edges contained in the two-phase pulse trains(XA, XB). Therefore, the two-phase pulse train including phasecomponents XA and XB has a composite period of 8 μs. The timing of thetwo-phase pulse trains (XA, XB) is regulated by clock signals T1 and T2.The clock signal T2 determines the timing of a packet of four datavalues in one transaction processing, and is set to T2=5ms in thisembodiment. In this case, the data transaction rate is accordingly setto 200 packet/sec.

A CPU of the transmitter is interrupted temporarily by an interruptsignal INT at a trailing edge a of the signal T1 so that the CPU checksthrough its CPU port a logic level of the other clock signal T2. Whenthe signal T2 is at level L, a first data value is latched into the8-bit latching circuit 20. On the other hand, when the signal T2 is atlevel H, a second data value is latched into the 8-bit latching circuit20. Then, the latched data value is loaded into the 8-bit binary counter21 to preset the same. The counter 21 starts at time b when the signalT1 turns to the H level to count the clock pulses CK until the countednumber of the clock pulses reaches a certain integral value preset inthe counter 21. The counter 21 holds a signal CY at time c when theclock pulses have been counted. Operation of the phase circuit 19 isstarted by the clock pulse signal CK at a time d during the course ofthe operation of the 8-bit binary counter 21 to generate the X two-phasepulse trains (XA, XB). The other Y pulse circuit 16 has a similarstructure as that of the X pulse circuit 15. However, the Y pulsecircuit 16 is provided with an inverter 24 for inverting the phasecondition of Y two-phase pulse train (YA, YB) relative to thecorresponding X two-phase pulse train.

FIG. 7 includes a series of waveforms of the thus formed X two-phasepulse train and Y two-phase pulse train. In FIG. 7, the X pulse traincorresponds to the integral value "1" of the given X data, and the Ypulse train corresponds to another integral value "-7" of the given Ydata.

Next, FIG. 8 is a diagram of the receiver hardware construction. Thereceiver, such as a host computer, is provided with a mouse interface.The mouse interface includes a mouse counter 25 and a port 26. The mousecounter 25 includes an X counter for counting the X two-phase pulsetrains (YA, YB) and a Y counter for counting the Y two-phase pulsetrains (YA, YB). The port 26 normally responds to switching signals S1and S2 of a type usually derived from a bus mouse. Since the bus mousein accordance with the present invention does not derive switchingsignals of the usual type, port 26 is not used in the inventivecommunication system. However, it is possible to control the retrievaltime of a transferred data value by using normal switching signals S1and S2. Applicants have already disclosed such data communication systemutilizing the port 26 in Japanese Patent Application No. 181438/1989.However, the port 26 is usually provided with a delay circuit forpreventing chattering of the switching signals S1 and S2 to therebyhinder fast data transfer. The host computer of the receiver furtherincludes a CPU 27 for retrieving a counted value of the mouse counter25.

FIG. 9 is a flow chart of the retrieval process of the mouse counter, asconducted by the receiver host computer. In this embodiment, a set offour data values is transferred as one data packet in first and secondperiods. Namely, the first pair of X and Y data values and the secondpair of X and Y data values are sequentially supplied to the hostcomputer as one complete data packet. When the first data pair isadmitted, the CPU 27 reads out the X counter. If the X data value ispositive, the CPU 27 sums the fragmentally counted contents of the Xcounter until the last count turns to null. On the other hand, if the Xdata value is negative, the computer jumps to error processing. The CPU27 also reads out intermittently the content of the Y counter. If the Ydata value is negative, the CPU 27 sums the intermittently retrievedcontents of the Y counter until the Y counter turns to zero. On theother hand, if the Y data value is positive, the computer jumps to errorprocessing. When both of the X counter content and the Y counter contentare finally nulled, the CPU 27 determines that the first data transferhas been completed and proceeds to a receiving process of the seconddata pair.

When the second data pair is admitted, the X counter is intermittentlyread out. If the X data value is negative, the sum of the contents iscarried out until the last counter value is zero. Otherwise, if the Xdata value is positive, the computer jumps to error processing. The Ycounter is also checked intermittently. If the Y data value is positive,the sum of the Y counter value is carried out until the last countervalue is zero. Otherwise, if the Y data value is negative, the computerjumps to error processing. When the X counter content and Y countercontent both turn to zero, a judgement is made that the transmitter hasfinished transferring the second data pair, thereby confirmingcompleteness of the transferred packet of four data values. Then, theretrieval processing returns to an initial admission step for the nextfirst data pair.

Next, the description is given for the data transaction rate of theinventive pulse count mode communication system for the case of a packetof four data values transferred during processing of one transaction.The transaction rate is determined according to the transmitter pulsetrain frequency and retrieval frequency of the mouse counter in thereceiver. If the receiver has an internal timer to set an internal timeinterval of 2 ms, one packet of four data values can be transferredduring a transaction period of 5×2=10 ms. Thus, the transaction rate is100 packets/sec. The shorter the period of the pulse train outputtedfrom the transmitter and the shorter the sample timing of the mousecounter in the receiver, the faster the transaction rate. Preferably,either the period of the pulse train or the sampling interval may bevariably set to realize a desired transaction rate. The following TABLE2 shows the relation between the receiver internal timer rate and thetransaction rate.

                  TABLE 2                                                         ______________________________________                                                       Transfer period                                                                           Retrieving                                         Data transaction                                                                             (ms)        interval (ms)                                      rate (pps)     Transmitter Receiver                                           ______________________________________                                        100            5           2                                                  200            2.5         1                                                  ______________________________________                                    

Lastly, a description is given below for an example of a data packetformat transferred according to the inventive data communication system.It is assumed that an exemplary digital data packet indicative of acoordinate point inputted by a digitizer is transferred to a hostcomputer. The digital data packet is comprised of two or more of bytes,depending on the digitizer size. For example, in the following TABLE 3are shown bit and byte formats of a digital data packet comprised offirst through fourth bytes each containing eight parallel bits.

                  TABLE 3                                                         ______________________________________                                        7      6        5      4     3    2     1    0                                ______________________________________                                        1    --    RDY      S 5  S 4   S 3  S 2   S 1  S 0                            2    --    Y 9      Y 8  Y 7    X 10                                                                              X 9   X 8  X 7                            3    --    X 6      X 5  X 4   X 3  X 2   X 1  X 0                            4    --    Y 6      Y 5  Y 4   Y 3  Y 2   Y 1  Y 0                            ______________________________________                                    

In the TABLE 3, the left column numerals 1-4 denote the first throughfourth bytes, respectively, and the top row numerals 7-0 denote aneight-bit arrangement in each of the bytes. In this example, the mostsignificant bit position is vacant in each byte. Accordingly, theinformation of one coordinate point is represented by a multiple bitarrangement of 4×7=28. This 28-bit arrangement is divided into the firstthrough fourth bytes. The bits XO through X10 denote an X coordinatevalue having integral values of 0 through 2047. The bits Y0 through Y9denote a Y coordinate value having integral values of 0 through 1023.Further, the bits S0 through S5 represent a switching signal related toa kind of input tool used to designate a coordinate point and togradation information of the designated point. The bit RDY indicateswhether a coordinate designating tool exists within an effective area ofthe planar sensor.

In the above described embodiment, the coordinate data value inputtedfrom the digitizer is transferred to the host computer. Generally, theinventive pulse count mode communication system can be applied to datatransfer between various types of input terminal devices and measurementdevices, and the host computer. Therefore, the technical scope of thepresent invention is not limited to data transfer from the digitizer.

In the above described embodiment, the digitizer absolute coordinatedata value is transferred by means of the inventive pulse count modecommunication system. However, the present invention is not limited tothis embodiment, but the invention may be applied to transactioninvolving a relative coordinate data in similar manner. The descriptionof FIG. 15 is given for processing the displacement of a coordinatedesignating tool, with data transfer from the digitizer to the hostcomputer by means of the aforementioned hardware construction by using atwo-phase pulse train. In the present embodiment, the transmittertransmits a pair of relative X and Y coordinate data value every giventransfer period having an interval of, for example, 10 ms, while thereceiver retrieves the pair of X and Y data values every given retrievalperiod having another interval of, for example, 8 ms, which is smallerthan the transfer interval. Any receiving misoperation, such as overflowof the mouse counter, can be avoided by such settings of communicationtimings.

Aside from the above, a bus mouse device produces a two-phase pulsetrain as shown in FIG. 14. In detail, as illustrated in FIG. 13, the busmouse device generates two-phase pulse trains having a variable pulsewidth determined according to the rotation speed of a sensor coupled toa rotary shaft. Therefore, the pulse width varies as the bus mousemoves. The pulse train is not interrupted as long as the bus mouse ismoving. On the other hand, according to the present invention, thereceiver, i.e., the host computer, is provided with a mouse counterresponsive only to count pulse edges without regard to the fact that thepulse train is continuous or interrupted, or the pulse width varies oris constant, until the CPU retries the counted value of the mousecounter. Therefore, it is not necessary to form two-phase pulse trainsthat are transferred by the inventive system identically to thoseproduced by the typical bus mouse. Accordingly, the pulse circuitprovided in the transmitter of the inventive system can be utilized fortransferring a relative displacement data value from the digitizer suchthat the two-phase pulse trains are intermittently outputted everytransfer period of 10 ms as shown in FIG. 15. In turn, the host computereffects the retrieval every 8 ms period to avoid overflow of the mousecounter. By such a timing relation, the relative displacement data valuecan be transferred from a coordinate input device, such as a digitizer,to the host computer.

In practical use of the digitizer, it is desired to selectively transferto the host computer either the absolute coordinate data value or therelative coordinate data value or the relative displacement data value.Thus, there is described infra a modified communication system effectiveto select either the absolute coordinate data value or the relativecoordinate data value so as to transfer the selected data value to thebus mouse interface provided in the host computer by means of commonhardware.

FIG. 16 is a hardware construction diagram of a transmitter operative toswitch between the absolute coordinate data value and the relativecoordinate data value to be transferred. This hardware is comprised of Xpulse circuit 15 and Y pulse circuit 16 corresponding, respectively, toan X counter and a Y counter provided in the receiver, and a timingcircuit 17 for deriving a pulse train. The X pulse circuit 15 and Ypulse circuit 16 have the same construction for outputting X two-phasepulse trains (XA, XB) and Y two-phase pulse trains (YA, YB).

As shown in FIG. 16, the X pulse circuit 15 is comprised of a pulsegenerating circuit 18 operatively based on an 8-bit coordinate datavalue and 1-bit code fed from a 16-bit data bus DB connected to a CPU(not shown) of the digitizer for generating a primary pulse trainrepresenting a numerical value indicative of the fed data value, and aphase circuit 19 responsive to the primary pulse train to generate Xtwo-phase pulse trains (XA and XB). The pulse generating circuit 18 iscomprised of a 9-bit latching circuit 201 for sequentially latching adata value from the data bus DB, and an 8-bit binary counter 21operative according to an integral value determined by the binaryrepresentation of the eight least significant eight bits of the latched9-bit data value in the latching circuit 20 for counting a clock pulsesignal CK. Accordingly, the primary pulse train containing the countednumber of clock pulses is fed to the phase circuit 19 through a NANDcircuit 28. The phase circuit 19 is provided with a pair of D-flip-flops22, 23 responsive to a plus or minus code indicated by the mostsignificant bit T2 of the latched 9-bit parallel data value forproducing two-phase pulse trains (XA, XB) having relative advancing(leading) or delaying (lagging) phase conditions and representative ofthe least significant eight bits.

The pulse generating circuit 18 of the transmitter shown in FIG. 16includes multiple hardware components. However, the present invention isnot limited to such construction; e.g. a one chip CPU can be used toform a counter for generating a pulse train. FIG. 17 is a timing chartillustrative of the operation of such pulse generating means. As shownin the figure, the pulse generating means is comprised of a one-shotcounter operative to provide a one-shot pulse having a durationdetermined according to the coordinate data value to be transferred.During the one-shot pulse, a clock pulse signal CK having a period of 2μs passes through a gate circuit to the phase circuit. The phase circuitoutputs two-phase pulse train (XA, XB) having a definite number of pulseedges corresponding to the number of the inputted clock pulses. Suchconstruction simplifies the transmitter circuit structure.

Lastly, referring to FIG. 18, the description is given for the transferof relative displacement data values. When the digitizer CPU selects thetransfer of a relative displacement data value, the pulse circuit ofFIG. 16 operates according to the predetermined algorithm to generate apair of two-phase pulse trains indicative of the relative displacementdata value in a manner similar to a typical bus mouse device.

With regard to the transfer of the absolute coordinate data, the CPU ofthe digitizer is temporarily interrupted in response to a trailing edgeof the signal T1 so that the CPU writes the data value into the pulsecircuit. However with regard to the transfer of the relative coordinatedata value, the data value is loaded into the pulse circuit in responseto a clock of an internal timer in the digitizer. Namely, as shown inFIG. 18, firstly the digitizer and the bus mouse interface areinitialized to switch the digitizer operation program to the relativecoordinate data transfer mode. Next, a pair of relative displacements dXand dY are calculated every given 10 ms period, based on the detectionresults of successive absolute coordinate points in the digitizer, andthe calculated data pair of dX and dY are loaded into the respective Xand Y pulse generating circuits. As opposed to the transfer of theabsolute coordinate data value, the pair of relative displacement datavalues dX and dY in a range of +127 through -128 are concurrentlywritten into the pair of X and Y pulse generating circuits,respectively, without employing a specific procedure. If the relativedisplacement data value is positive, the most significant bit is set toL level in the 9-bit latching circuit 201 shown in FIG. 16 and the eightlower order bits have values determined by the value of the relativedisplacement dX or dY. Otherwise if the relative displacement data valueis negative, the most significant bit is set to H level in the 9-bitlatching circuit 201 and the eight lower order bits have valuesrepresenting the relative displacement dX or dY. Although the switchingsignals S1 and S2 related to a bus mouse device are not used in theabsolute coordinate data transfer, in the relative coordinate datatransfer the switching signals S1 and S2 are outputted to designate aswitch condition of the coordinate input tool so as to enable the sameto simulate a typical bus mouse device. By using this two-phase pulsegenerating circuit, the CPU of the digitizer can be efficiently operatedto simply set up a relative displacement data value at a desired timeinterval. The transmitted data value is retrieved each retrievalinterval of, for example, 8 ms, which is selected to be shorter than thetransfer period of, for example, 10 ms.

INDUSTRIAL APPLICABILITY

As described above, the inventive pulse count mode communication systemcan be applied to transfer a coordinate data value inputted by acoordinate input device, such as a digitizer, to a host computer inwhich the transferred data is to be processed. Further, the inventivesystem can be generally applied to a parallel bit data transfer betweena host computer and various types of peripheral input terminal devicesand measurement devices.

We claim:
 1. A communication system for transferring parallel binary data bits from a transmitter to a receiver, the transmitting comprising: a pulse circuit operative each given transfer period for outputting a two-phase pulse train including a certain number of pulse edges corresponding to an integral number represented by binary parallel bits constituting the data to be transferred; the receiver comprising: a resettable counting circuit for counting pulse edges contained in the transferred two-phase pulse train, and a retrieving circuit operative intermittently every given retrieving interval within one transfer period for retrieving sequentially each counted content from the counting circuit and repreatedly resetting the content of the counting circuit, and being operative when a last counted content turns to a preset value for summing up all of the sequentially retrieved counted contents to thereby determine a received number of the pulse edges representative of the transferred data.
 2. A communication system according to claim 1, wherein the transmitter includes a coding circuit for applying to a sequence of plural data either of a plus code and a minus code effective to discriminate the plural data from each other, and the pulse circuit operates to switch a phase condition of the two-phase pulse train according to the code applied to the corresponding data, and wherein the receiver operates to discriminate from each other the time-sequentially transferred plural data according to the phase condition of each two-phase pulse train.
 3. A communication system according to claim 2, wherein the coding circuit operates to apply the plus code and the minus code alternately to the sequence of the plural data.
 4. A communication system according to claim 2, wherein the coding circuit operates to apply one code to a top data in the sequence and to apply the other code to subsequent data in the sequence.
 5. A communication system according to claim 1, wherein the transmitter includes a pair of pulse circuits for concurrently transmitting a pair of data, and the receiver includes a corresponding pair of counting circuits for concurrently receiving a pair of data.
 6. A communication system according to claim 5, wherein the pair of pulse circuits operate to transmit a pair of data in a first transfer period and to transmit another pair of data in a second transfer period to thereby effect transaction of one data packet containing four data.
 7. A communication system according to claim 1, wherein the counting circuit and the retrieving circuit together constitute a bus mouse interface in the receiver.
 8. A communication system according to claim 1, wherein the transmitter includes a coordinate input device operative to designate a coordinate data to be transferred.
 9. A communication system according to claim 1, wherein the transmitter includes a coordinate input device operative to selectively produce an absolute coordinate data value and a relative coordinate data value, and selecting means for at different times selecting the absolute coordinate data value and the relative coordinate data value to be transferred.
 10. A communication system according to claim 9, wherein the retrieving circuit of the receiver operates each given retrieving period set no greater than the transfer period for detecting a selected relative coordinate data transferred from the transmitter every transfer period.
 11. A communication system according to claim 9, wherein the transmitter operates to calculate the relative coordinate data value based on the absolute coordinate data value directly obtained by the coordinate input device, and wherein the coding circuit operates to selectively apply a plus code and a minus code to the calculated relative coordinate data value and the pulse circuit operates according to the coded relative coordinate data value for producing a two-phase pulse train having a certain phase condition according to the applied code so as to simulate a typical bus mouse device.
 12. A receiver responsive to parallel binary data bits transmitted from a transmitter during a given transfer period as a two-phase pulse train including a certain number of pulses corresponding to an integral number represented by binary parallel bits constituting a transmitted data value; the receiver comprising: a resettable counting circuit for counting pulses contained in the two-phase pulse train as received at the receiver, and a retrieving circuit operative intermittently every given retrieving interval within one transfer period for retrieving sequentially each counted content from the counting circuit and repeatedly resetting the content of the counting circuit, and being operative when a counted content turns to a predetermined value for summing up all of the sequentially retrieved counted contents to thereby determine a received number of the pulse edges representative of the transmitted data value.
 13. The receiver of claim 12 wherein the counting circuit and the retrieving circuit together constitute a bus mouse interface.
 14. The receiver of claim 12 wherein the transmitted data bits during a first period represent absolute coordinate data value and during a second period represent a relative coordinate data value, the retrieving circuit operating during each given retrieving period no greater than the transfer period for detecting the absolute coordinate data value transmitted during the transfer period.
 15. A transmitter responsive to a signal representing a sequence of plural data values comprising a pulse circuit operative during each of plural transmitting periods for deriving a two-phase pulse train including a certain number of pulse edges corresponding to an integral number represented by binary parallel bits constituting data to be transmitted, a coding circuit coupled with the pulse circuit for selectively applying to signal representing the sequence of plural data values a plus code and a minus code that effectively discriminates the plural data values from each other, the pulse circuit operating to switch a phase condition of the two-phase pulse train according to the code selectively applied to the sequence of plural data values.
 16. The transmitter of claim 15 wherein the coding circuit operates to apply the plus code and the minus code alternately to the sequence of the plural data values.
 17. The transmitter of claim 15 wherein the coding circuit operates to apply one code to a first data value in the sequence and to apply the other code to subsequent data value in the sequence.
 18. The transmitter of claim 15 wherein a pair of said pulse circuits are included for concurrently transmitting a pair of data values, the pair of pulse circuits operating to transmit a pair of data values in a first transfer period and to transmit another pair of data values in a second transfer period to thereby effect transaction of one data packet containing four data values.
 19. The transmitter of claim 15 further including a coordinate input device operative to designate a coordinate data value to be transmitted.
 20. The transmitter of claim 15 further including a coordinate input device operative to selectively produce an absolute coordinate data value and a relative coordinate data value, and selecting means coupled with the coordinate input device and the coding circuit for at different times selecting the absolute coordinate data value and the relative coordinate data value to be transmitted.
 21. The transmitter of claim 15 wherein the transmitter operates to calculate a relative coordinate data value based on absolute coordinate data value directly obtained by a coordinate input device, and wherein the coding circuit operates to selectively apply either a plus code or a minus code to the calculated relative coordinate data value and the pulse circuit operates according to the coded relative coordinate data value for producing a two-phase pulse train having a certain phase condition according to the applied code so as to simulate a typical bus mouse device. 